Patrick Iff, Maciej Besta, Matheus Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
(In Proceedings of the 60th Annual Design Automation Conference, Jul. 2023)
Abstract
Chips with hundreds to thousands of cores require scalable networks-on-chip (NoCs). Customization of the NoC topology is necessary to reach the diverse design goals of different chips. We introduce sparse Hamming graph, a novel NoC topology with an adjustable costperformance trade-off that is based on four NoC topology design principles we identified. To efficiently customize this topology, we develop a toolchain that leverages approximate floorplanning and link routing to deliver fast and accurate cost and performance predictions. We demonstrate how to use our methodology to achieve desired cost-performance trade-offs while outperforming established topologies in cost, performance, or both.
Documents
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BibTeX
@inproceedings{, author={Patrick Iff and Maciej Besta and Matheus Cavalcante and Tim Fischer and Luca Benini and Torsten Hoefler}, title={{Sparse Hamming Graph: A Customizable Network-on-Chip Topology}}, year={2023}, month={Jul.}, booktitle={Proceedings of the 60th Annual Design Automation Conference}, source={http://www.unixer.de/~htor/publications/}, }
